US Patent Issued to AEM SINGAPORE on Sept. 21 for " Cold plate with porus thermal conductive structure" (Singaporean Inventors)

• THERMAL TEST HEAD FOR AN INTEGRATED CIRCUIT DEVICE

  Publication number:  20210325452

  Abstract:  A thermal test head for an integrated circuit device includes a heat exchanger assembly, a contact assembly configured to contact the integrated circuit, and a thermal control assembly disposed between the heat exchanger assembly and the contact assembly. The thermal control assembly includes a Peltier device in thermal contact with opposing surfaces of the heat exchanger assembly and the contact assembly, and a spacer in physical contact with the opposing surfaces of the heat exchanger assembly and the contact assembly.

  Type:  Application

  Filed:  September 16, 2020

  Publication date:  October 21, 2021

  Applicant:  AEM SINGAPORE PTE LTD

  Inventors:  See Jean CHAN, Zhaomeng WANG, Yao Kun Leonard MAK, MuralliKrishna GOVINDANDHANASEKARAN

• THERMAL TEST HEAD FOR AN INTEGRATED CIRCUIT DEVICE

  Publication number:  20210325453

  Abstract:  A thermal test head for an integrated circuit device includes a heat exchanger assembly, a contact assembly configured to contact the integrated circuit, and a thermal control assembly disposed between the heat exchanger assembly and the contact assembly. The thermal control assembly includes a Peltier device in thermal contact with opposing surfaces of the heat exchanger assembly and the contact assembly, and a spacer in physical contact with the opposing surfaces of the heat exchanger assembly and the contact assembly.

  Type:  Application

  Filed:  September 16, 2020

  Publication date:  October 21, 2021

  Applicant:  AEM SINGAPORE PTE LTD

  Inventors:  See Jean CHAN, Zhaomeng WANG, Yao Kun Leonard MAK, MuralliKrishna GOVINDANDHANASEKARAN

• Cold plate with porus thermal conductive structure

  Patent number:  11129297

  Abstract:  A cold plate may include a plate body having a thermal conductive side a plurality of parallel hollow fluid channels running inside the plate body at least one fluid inlet in direct fluid communication with a first subset of the plurality of parallel hollow fluid channels at least one fluid outlet in direct fluid communication with a second subset of the plurality of parallel hollow fluid channels and a porous thermal conductive structure which fluidly connect the first subset of the plurality of parallel hollow fluid channels to the second subset of the plurality of parallel hollow fluid channels, and which is in thermal contact with the thermal conductive side of the plate body. The porous thermal conductive structure may include a plurality of elongate fluid contact surface regions, each may be extending continuously lengthwise along a longitudinal side of respective fluid channel to serve as a fluid interface.

  Type:  Grant

  Filed:  January 28, 2020

  Date of Patent:  September 21, 2021

  Assignee:  AEM SINGAPORE PTE. LTD.

  Inventors:  See Jean Chan, Zhaomeng Wang

• System and method for temporal signal measurement of device under test (DUT) and method of forming system

  Patent number:  10989758

  Abstract:  A measurement system of a device under test (DUT) includes a reference clock synthesizer configured to generate a master reference clock signal, a transmitter unit connected to the reference clock synthesizer and configured to connect to the DUT, and a measurement control system connected to the transmitter unit and configured to control the transmitter unit to generate a test signal pattern based on a first reference clock signal derived from the master reference clock signal, and generate a signal for passing through the DUT based on the test signal pattern. A receiver unit connected to the reference clock synthesizer is configured to connect to the DUT and to detect the signal and generate a digital signal based on the signal and a second reference clock signal derived from the master reference clock signal. The measurement control system is configured to provide an output signal based on the digital signal.

  Type:  Grant

  Filed:  September 19, 2019

  Date of Patent:  April 27, 2021

  Assignee:  AEM SINGAPORE PTE. LTD.

  Inventors:  Harshang Nileshkumar Pandya, Xing Zhu, Arvindbhai Chimanbhai Patel, Minglei Cui

• Configurable electronic device tester system

  Patent number:  9927478

  Abstract:  A configurable electronic test system that is adapted for varying test processes and thermal conditions, consisting of a device handler working with multiple testers and a thermal environment module for controlling the thermal condition during test. The test system can be easily expanded by stacking more testers vertically for more test capacity without requiring an increase in floor space.

  Type:  Grant

  Filed:  October 27, 2015

  Date of Patent:  March 27, 2018

  Assignee:  AEM SINGAPORE PTE. LTD.

  Inventors:  Boon Hua How, Kok Keong Ong, Chiang Huan Saw, See Jean Chan, Wee Tick Lo